The present invention generally relates to stacked gate memory devices such as an array of flash memory cells, and relates more particularly to a method of forming a stacked gate flash memory cell having a feature dimension which may be less than a feature dimension capable of being formed using conventional lithography processes.
As is generally known, in recent years a new category of electrically erasable EPROMs/EEPROMs has emerged as an important non-volatile memory which combines the advantages of EPROM density with EEPROM electrical erasability and are sometimes referred to as xe2x80x9cflashxe2x80x9d EPROM or EEPROM. Flash memory devices typically include multiple individual components formed on or within a substrate. Such devices often comprise a high density section and a low density section. For example, as illustrated in prior art FIG. 1A, a memory device such as a flash memory 10 comprises one or more high density core regions 11 and a low density peripheral portion 12 on a single substrate 13. The high density core regions 11 typically consist of at least one Mxc3x97N array of individually addressable, substantially identical floating-gate type memory cells and the low density peripheral portion 12 typically includes input/output (I/O) circuitry and circuitry for selectively addressing the individual cells (such as decoders for connecting the source, gate and drain of selected cells to predetermined voltages or impedances to effect designated operations of the cell such as programming, reading or erasing).
The memory cells within the core portion 11 are coupled together in a NOR-type circuit configuration, such as, for example, the configuration illustrated in prior art FIG. 1B. Each memory cell 14 has a drain 14a, a source 14b and a stacked gate 14c. 
The NOR configuration illustrated in FIG. 1B has each drain terminal 14a of the transistors within a single column connected to the same bit line (BL). In addition, each flash cell 14 has its stacked gate terminal 14c coupled to a different word line (WL) while all the flash cells in the array have their source terminals 14b coupled to a common source terminal (CS). In operation, individual flash cells may be individually addressed via the respective bit line and word line using peripheral decoder and control circuitry for programming (writing), reading or erasing functions.
Prior art FIG. 1C represents a fragmentary cross section diagram of a typical memory cell 14 in the core region 11 of prior art FIGS. 1A and 1B. Such a cell 14 typically includes the source 14b, the drain 14a, and a channel 15 in a substrate or P-well 16; and the stacked gate structure 14c overlying the channel 15. The stacked gate 14c further includes a thin gate dielectric layer 17a (commonly referred to as the tunnel oxide) formed on the surface of the P-well 16. The stacked gate 14c also includes a polysilicon floating gate 17b which overlies the tunnel oxide 17a and an interpoly dielectric layer 17c overlies the floating gate 17b. The interpoly dielectric layer 17c is often a multilayer insulator such as an oxide-nitride-oxide (ONO) layer having two oxide layers sandwiching a nitride layer. Lastly, a polysilicon control gate 17d overlies the interpoly dielectric layer 17c. The control gates 17d of the respective cells 14 that are formed in a lateral row share a common word line (WL) associated with the row of cells (see, e.g., prior art FIG. 1B). In addition, as highlighted above, the drain regions 14a of the respective cells in a vertical column are connected together by a conductive bit line (BL). The channel 15 of the cell 14 conducts current between the source 14b and the drain 14a in accordance with an electric field developed in the channel 15 by the stacked gate structure 14c. 
According to conventional operation, the flash memory cell 14 operates in the following manner. The cell 14 is programmed by applying a relatively high voltage VG (e.g., approximately 9 volts) to the control gate 17d and connecting the source to ground and the drain 14a to a predetermined potential above the source 14b (e.g., approximately 5 volts). These voltages generate a vertical and lateral electric field along the length of the channel from the source to the drain. This electric field causes electrons to be drawn off the source and begin accelerating toward the drain. As they move along the length of the channel, they gain energy. If they gain enough energy, they are able to jump over the potential barrier of the oxide into the floating gate 17b and become trapped in the floating gate 17b since the floating gate 17b is surrounded by insulators (the interpoly dielectric 17c and the tunnel oxide 17a). As a result of the trapped electrons, the threshold voltage of the cell 14 increases, for example, by about 2 to 5 volts. This change in the threshold voltage (and thereby the channel conductance) of the cell 14 created by the trapped electrons is what causes the cell to be programmed.
To read the memory cell 14, a predetermined voltage VG that is greater than the threshold voltage of an unprogrammed or erased cell, but less than the threshold voltage of a programmed cell, is applied to the control gate 17d with a voltage applied between the source 14b and the drain 14a (e.g., tying the source 14b to ground and applying about 12 volts to the drain 14a). If the cell 14 conducts (e.g., about 50-100 xcexcA), then the cell 14 has not been programmed (the cell 14 is therefore at a first logic state, e.g., a zero xe2x80x9c0xe2x80x9d). Likewise, if the cell 14 does not conduct (e.g., considerably less current than 50-100 xcexcA), then the cell 14 has been programmed (the cell 14 is therefore at a second logic state, e.g., a one xe2x80x9c1xe2x80x9d). Consequently, one can read each cell 14 to determine whether it has been programmed (and therefore identify its logic state).
A flash memory cell 14 can be erased in a number of ways. In one arrangement, a relatively high voltage VS (e.g., approximately 12-20 volts) is applied to the source 14b and the control gate 17d is held at a ground potential (VG=0), while the drain 14a is allowed to float. Under these conditions, a strong electric field is developed across the tunnel oxide 17a between the floating gate 17b and the source 14b. The electrons that are trapped in the floating gate undergo Fowler-Nordheim tunneling through the tunnel oxide 17a to the source 14b. In another arrangement, applying a negative voltage on the order of minus 10 volts to the control gate, applying 5 volts to the source and allowing the drain to float can also erase a cell. In a further arrangement, applying 5 volts to the P-well and minus 10 volts to the control gate while allowing the source and drain to float erases a cell.
In order to reduce memory costs, designers are constantly seeking ways to reduce a size of an individual flash memory cell in order to increase the memory density and therefore decrease the unit cost per bit. Unfortunately, a size of a flash memory cell is often limited by the lithography capabilities of the manufacturing process. For example, as illustrated in FIG. 1C, a width 19 of the stacked gate cell is limited by the lithography resolution of the stepper system. For example, in present day manufacturing processes, a feature dimension can be produced reliably at a feature size of about 0.13 micron. In order to further reduce cell size and therefore increase memory density and decrease the unit cost per bit, it would be desirable to create a memory cell having a width that is less than the capability of present day lithography processes, for example, of a dimension of about 100 nm (0.10 micron) or less.
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is intended neither to identify key or critical elements of the invention nor to delineate the scope of the invention. Its primary purpose is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
The present invention relates to a method of forming a stacked gate flash memory cell. The width of the flash memory cell is reduced to dimensions which are less than the feature resolution of lithography systems by employing a sidewall spacer as a hard mask to pattern the flash memory cell stack.
In accordance with one aspect of the present invention, a memory cell layer stack is formed by successive formation of a tunnel oxide layer, a first conductive layer, an interpoly dielectric layer and a second conductive layer, respectively. A sacrificial layer is then formed over the second conductive layer, and the sacrificial layer is patterned to form a sacrificial layer feature having a lateral sidewall edge associated therewith. A sidewall spacer is then formed adjacent the lateral sidewall edge, and the sidewall spacer is then employed as a hard mask to pattern the memory cell layer stack to form a stacked gate flash memory cell, wherein a width associated therewith is a function of the spacer width.
In accordance with another aspect of the present invention, the formation of the sacrificial layer comprises forming a dummy oxide layer over the second conductive layer followed by the formation of an antireflective coating thereover, for example, a nitride type layer. The patterning of the sacrificial layer then comprises patterning the antireflective coating to form a feature having a lateral edge sidewall. The sidewall spacer is then formed adjacent the lateral edge sidewall of the antireflective coating feature by depositing a spacer material thereover and performing a generally anisotropic etch thereof, thereby substantially removing the spacer material overlying the dummy oxide and a top portion of the antireflective coating feature, and leaving spacer material adjacent the sidewall edge. The antireflective coating feature is then removed, leaving the sidewall spacer overlying the dummy oxide layer. The sidewall spacer is then employed to pattern the dummy oxide material, and the sidewall spacer and patterned dummy oxide together act as a hard mask in the subsequent patterning of the memory cell stack.
In accordance with still another aspect of the present invention, a method of patterning a stacked gate flash memory cell comprises successively forming a tunnel oxide, a first polysilicon layer (a poly1 of floating gate layer), an oxide-nitride-oxide (ONO) layer, and a second polysilicon layer (a poly2 or control gate layer) to form a memory cell layer stack. A dummy oxide material (or other material substantially selective with respect to underlying layers in an etch process of the stack) is formed thereover, followed by the formation of an antireflective coating such as a nitride material.
The antireflective coating is subsequently patterned, for example, via a standard patterned photoresist, wherein the antireflective coating minimizes standing wave phenomena due to exposure reflections, to formed a patterned antireflective coating having a lateral sidewall edge and a feature size which is as small as the lithography system permits. A spacer layer, such as a polysilicon layer, is then formed over the patterned antireflective coating and etched in a generally anisotropic manner to form a poly sidewall spacer adjacent the lateral sidewall edge of the patterned antireflective coating. The width of the poly sidewall spacer is a function of a thickness of the deposited polysilicon layer over the antireflective coating and may be less than a feature width capability of the lithography system (e.g., 100 nm or less). The patterned antireflective coating is removed, and the dummy oxide material is patterned using the poly spacer as a hard mask. The poly2 layer is then etched using both the poly spacer and the patterned dummy oxide as a hard mask (wherein the poly2 patterning substantially deteriorates or removes the poly spacer). The patterned dummy oxide is then employed to complete the patterning of the ONO and poly1 layer to fabricate a stacked gate flash memory cell having a width which is a function of the poly spacer width, which may be less than a feature size capability of the lithography system.
In accordance with yet another aspect of the present invention, a patterning of any type feature having a feature size less than a capability of a lithography system is provided. The method comprises forming a first layer over a substrate, and forming a second layer over the first layer. The second layer is patterned, for example, using conventional lithography to form a structure having a sidewall edge associated therewith and a third layer is formed over the patterned structure. The third layer is patterned, for example, using a generally anisotropic etch to form a sidewall spacer adjacent the sidewall edge of the second layer, and the patterned second layer structure is removed, leaving the sidewall spacer having a width associated therewith. The width of the sidewall spacer is a function of the thickness of the third (spacer) layer when formed, and may be less than a minimum feature size capability of a lithography system. The first layer is then patterned using the sidewall spacer as a hard mask to thereby form a first layer feature having a feature size which is a function of the sidewall spacer.